(1) Field of the Invention
The present invention relates to associative memory cells for associative memory devices, particularly to improved associative memory cells of low power consumption and capable of performing a high speed operation.
(2) Description of the Prior Art
With developments of recent electronic techniques, memory devices having various function are coming into wide use for electronic devices. An associative memory device is one such device.
FIG. 1 shows the construction of CMOS static associative memory cell according to the prior art (see, ISSCC-International Solid State Circuit Conference, Feb. 13, 1985, pp 42-43). The memory associative cell consists of a memory cell portion 101 for performing a normal storing function and an exclusive NOR portion 103 indicated as E.NOR in FIG. 1, which performs an Associative operation.
The cell portion 101 further comprises two CMOS inverter circuits connected so as to perform a flip-flop function and transfer gates 105 and 107 of N-channel MOS transistors (which are referred to hereinafter as NMOS transistors) which transfer data between each inverter circuit and each of bit lines BL and BL, each gate electrode thereof being connected to a word line WL.
The exclusive NOR portion 103 consists of NMOS transistors connected so as to construct wired AND circuits. In the associative memory cell thus constructed, when data retrieval operation as a basic function of the associative memory should be performed, the bit lines BL and BL are preliminarily maintained a low level prior to the retrieval operation and a sense line SE is precharged to a power supply voltage V.sub.DD.
With this condition, the retrieval data or data and its inverted retrieval data in polarity are supplied to the bit lines BL and BL which have been predischarged to the ground level, i.e., OV, respectively. When the retrieval data on the bit lines BL and BL coincides with the stored data in the memory cell portion 101, the sense line SE is maintained at the voltage V.sub.DD, otherwise it is discharged to the low level, i.e., OV. This means that same data as the retrieval data has been stored in the memory cell connected to the sense line SE.
Furthermore, when the data stored in the cell portion 101 should be read out on the bit lines BL and BL, the bit lines are precharged to the power supply voltage V.sub.DD preliminarily, prior to the normal read operation. After the precharge of the bit lines BL and BL has been terminated, the word line WL connected to each gate electrode of the transfer gates 105 and 107 is maintained at the high level. The transfer gates 105 and 107 are then rendered conductive and the data stored in the memory cell portion 101 is read on the bit lines BL and BL through the gates 105 and 107.
In this manner as described, the potentials of the bit lines BL and BL prior to the start of the read operation are precharged to the power supply voltage V.sub.DD, while the bit lines BL and BL prior to the start of the retrieval operation are predischarged to the ground level. Namely, every time the operation mode of the associative memory is changed, the bit lines BL and BL are precharged or predischarged to the voltage V.sub.DD or to the ground level. As a result, electric power and the operation time for performing the precharge and predischarge are both required, thereby preventing the associative memory from being low power consumption as well as from performing at a high speed operation.
Even when the bit lines BL and BL are not precharged to the voltage V.sub.DD, but are predischarged to the ground level before starting the read operation, the data stored in the memory cell portion 101 can be read out. In this case, however, if the stored data having the high level is read out on the bit lines BL and BL from the output terminal of the inverter circuit through the transfer gate 105, the transfer gate 105 is rendered non-conductive when the voltage of the bit lines BL and BL are increased from the ground level (normally OV) to V.sub.DD -V.sub.T level (where V.sub.T indicates a threshold voltage of each of the NMOS transistors) because of the characteristics of the NMOS transistors as transfer gates.
Moreover, the increase in the source potential of the transfer gate 105 causes V.sub.T to be large because of so-called "back gate bias effect." This will prevent the potential of each of the bit lines BL and BL from increasing up to the necessary potential for sufficiently carrying out the read operation.
When further increase in the potentials of the bit lines causes the potential difference between the source and drain of the transfer gate 105, the speed of the potential increase of the bit lines becomes delayed. This in turn results in the delay in reading out the data from the memory cell portion 101 onto the bit lines BL and BL, thereby inviting a degradation in the characteristic of the read data due to the slow speed in the read operation.
Accordingly, when the read operation is performed with the bit lines BL and BL being predischarged to the ground level prior to the read operation, the precharge of the bit lines BL and BL can be dispensed with, for every operation mode. However, the circuit design must take into consideration degradation of the characteristic, thus making a large operating margin difficult.